Clock Selection Register (Ckscr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 5 CLOCKS
5.3

Clock Selection Register (CKSCR)

The clock selection register (CKSCR) switches among the main clock, sub-clock, and
PLL clock, and it selects the oscillation stabilization wait time and PLL clock
multiplication rate.
I Configuration of clock selection register (CKSCR)
Figure 5.3-1 "Configuration of clock selection register (CKSCR)" shows the configuration of the
clock selection register (CKSCR). Table 5.3-1 "Functions of bits in clock selection register
(CKSCR)" has explanations of the functions of bits in the clock selection register.
Figure 5.3-1 Configuration of clock selection register (CKSCR)
Address bit15
0000A1
Note
When reset, the machine clock selection (MCS) bit is initialized to the main clock selection.
118
bit14 bit13 bit12 bit11
SCM MCM WS1 WS0 SCS
H
R R R/W R/W R/W
HCLK : Oscillation clock
R/W : Read/write enabled
R : Read only
0 : Not used
: Initial value
bit8 bit7
bit10 bit9
MCS CS1 CS0 (LPMCR)
R/W R/W R/W
Multiplication rate selection bit
Values in ( ) are for 4 MHz
CS1 CS0
oscillation clock
1 × HCLK ( 4 MHz)
0 0
2 × HCLK ( 8 MHz)
0 1
3 × HCLK (12 MHz)
1 0
4 × HCLK (16 MHz)
1 1
MCS PLL clock selection bit
0 PLL clock selection
1 Main clock selection
Sub clock selection bit
SCS
0 Sub clock selection
1 Main clock selection
Oscillation stabilization wait time
selection bits
WS1 WS0
Values in ( ) are for 4 MHz
oscillation clock
/HCLK (about 256 µs)
0 0 2 10
13
2 /HCLK (about 2.05 ms)
0 1
15
1 0 2 /HCLK (about 8.19 ms)
17
1 1 2 /HCLK (about 32.77 ms)
* During a power-on reset, evaluation devices and
18
FLASH devices become 2 /HCLK (about 65.54 ms),
17
and mask devices become 2 /HCLK (about 32.77 ms).
PLL clock display bit
MCM
0 In use by PLL clock
1 In use by main clock or sub clock
Sub clock display bit
SCM
0 In use by sub clock
1 In use by main clock or PLL clock
bit0 Initial value
11111100
B