Ckscr (Clock Selection Register); Table 6.3.2A Ws Bit Settings - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

6.3.2 CKSCR (Clock selection register)

Clock selection register
Address: 0000A1
Read/write
Initial value
[Bit 15] SCM
This bit indicates whether the main clock or the subclock is selected as the machine clock. When this
bit is "0", it indicates that the subclock is selected; when this bit is "1", it indicates that the main clock is
selected. If SCS = 0 and SCM = 1, it indicates that the main clock oscillation stabilization waiting period
is in progress.
[Bit 14] MCM
This bit indicates whether the main clock or the PLL clock is selected as the machine clock. When this
bit is "0", it indicates that the PLL clock is selected; when this bit is "1", it indicates that the main clock is
selected. If MCS = 0 and MCM = 1, it indicates that the PLL clock oscillation stabilization waiting period
is in progress. Note that the PLL clock oscillation stabilization waiting period is fixed at 2
cycles.
[Bits 13, 12] WS1, WS0
These bits set the main clock oscillation stabilization waiting period upon wake-up from stop mode or
hardware standby mode is released.
These bits are initialized to "11" by a power-on reset; these bits are not initialized by a reset due to
other sources. These bits can be read and written.
WS1
[Bit 11] SCS
This bit selects either the main clock or the subclock as the machine clock. When a "0" is written to this
bit, the subclock is selected; when a "1" is written to this bit, the main clock is selected. If a "1" is
written to this bit while it is "0", the oscillation stabilization waiting period for the main clock is generated;
therefore, the timebase timer is automatically cleared. In addition, the subclock (as is) is used for the
operation clock when the subclock is selected. (When the source oscillation is 32 kHz, the operation
clock is 32 KHz.) When SCS and MCS are both set to "0", SCS takes priority and the subclock is
selected.
This bit is initialized to "1" by a reset due to power-on, hardware standby, the watchdog timer, an
external source, or software.
MB90580 Series
15 14
MCM WS1
SCM
H
(R) (R) (R/W)
(1) (1)

Table 6.3.2a WS Bit Settings

WS0
0 0
0 1 Approx. 1.02 ms (count of 2
1 0 Approx. 8.19 ms (count of 2
1 1 Approx. 65.54 ms (count of 2
13 12 11
WS0 SCS
(R/W) (R/W)
(1) (1) (1)
Oscillation stabilization waiting period
(source oscillation at 4 MHz)
No oscillation stabilization waiting period
Chapter 6: Low Power Control Circuit
6.3 Registers and register details
10 9 8
MCS CS1 CS0
(R/W) (R/W) (R/W)
(1) (0) (0)
14
of the source oscillation)
16
of the source oscillation)
18
of the source oscillation)
Bit No.
CKSCR
12
main clock
65