Clock Selection Register (Ckscr) And Pll Output Selection Register (Pllos) - Fujitsu MB90480 Series Hardware Manual

CHAPTER 5 CLOCKS
5.3 Clock Selection Register (CKSCR) and PLL Output
Selection Register (PLLOS)
The clock selection register (CKSCR) switches among the main clock, sub-clock, and
PLL clock, and it selects the oscillation stabilization wait time and PLL clock
multiplication rate.
The PLL output selection register (PLLOS) must be set for the PLL to be used when a
machine clock is used at a frequency of 20 to 25 MHz.
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Configuration of clock selection register (CKSCR)
Figure 5.3-1 shows the configuration of the clock selection register (CKSCR). Table 5.3-1 has
explanations for the functions of bits in the clock selection register.
Figure 5.3-1 Configuration of clock selection register (CKSCR)
Address bit15
0000A1
112
bit14 bit13 bit12 bit11
SCM MCM WS1 WS0 SCS
H
R R R/W R/W R/W
HCLK : Oscillation clock
R/W : Readable/Writable
R : Read only
- : Undefined
: Initial value
bit8 bit7
bit10 bit9
MCS CS1 CS0 (LPMCR)
R/W R/W R/W
Multiplication rate selection bit
Values in ( ) are for 4 MHz
CS1 CS0
oscillation clock
1 × HCLK ( 4 MHz)
0 0
2 × HCLK ( 8 MHz)
0 1
3 × HCLK (12 MHz)
1 0
4 × HCLK (16 MHz)
1 1
Note:
To ensure the internal circuit operation with
a frequency at 20 to 25 MHz, set the PLL2
bit of the PLLOS register to 1 to double the
above multiply-by rate. However, do not set
the PLL2 bit to 1 when CS1 = 1 and CS0 = 1.
MCS PLL clock selection bit
0
PLL clock selection
1
Main clock selection
SCS Sub clock selection bit
0
Sub clock selection
1 Main clock selection
Oscillation stabilization wait time
selection bits
WS1 WS0
Values in ( ) are for 4 MHz
oscillation clock
/HCLK (about 256 μs)
10
0 0 2
13
2 /HCLK (about 2.05 ms)
0 1
15
1 0 2 /HCLK (about 8.19 ms)
17
1 1 2 /HCLK (about 32.77 ms)
* During a power-on reset, evaluation devices and
18
FLASH devices become 2 /HCLK (about 65.54 ms),
17
and mask devices become 2 /HCLK (about 32.77 ms).
MCM PLL clock display bit
0
In use by PLL clock
1 In use by main clock or sub clock
Sub clock display bit
SCM
0 In use by sub clock
1 In use by main clock or PLL clock
bit0 Initial value
11111100
B