Transmitter Overview - Xilinx Virtex-5 RocketIO GTP User Manual

R
GTP Transmitter (TX)
This chapter shows how to configure and use each of the functional blocks inside the GTP
transmitter.

Transmitter Overview

Each GTP transceiver in the GTP_DUAL tile includes an independent transmitter, made
up of a PCS and a PMA.
data flows from the FPGA into the FPGA TX interface, through the PCS and PMA, and
then out the TX driver as high-speed serial data. Refer to
Design,"
9
7
TX
TX TX
OOB
Driver Preemp
&
PCI
8
Shared
PMA
PLL
Divider
From Shared PMA PLL
The key elements within the GTP transmitter are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Figure 6-1
for latency information on this block diagram.
Polarity
Control
PISO
6
TX-PMA TX-PCS
Figure 6-1: GTP TX Block Diagram
"FPGA TX Interface," page 90
"Configurable 8B/10B Encoder," page 98
"TX Buffering, Phase Alignment, and Buffer Bypass," page 102
"TX Polarity Control," page 108
"TX PRBS Generator," page 109
"Parallel In to Serial Out (PISO)," page 110
"Configurable TX Driver," page 112
"PCI Express Receive Detect Support," page 116
"TX OOB/Beacon Signaling," page 119
www.xilinx.com
shows the functional blocks of the transmitter. Parallel
4
Phase
Adjust
FIFO
3
5
PRBS
Generator
Chapter 6
Appendix E, "Low Latency
1
2
8B/10B
Encoder
FPGA
Interface
TX PIPE Control
UG196_c6_01_042407
TX
89