Data Path Latency; Table 3-4: Latency Through Various Transmitter Components/Processes; Table 3-5: Latency Through Various Receiver Components/Processes - Xilinx RocketIO X User Manual

Clock Domain Architecture

Data Path Latency

With the many configurations of the Virtex-II Pro X transceiver, both the transmit and
receive latency of the data path varies.
latencies for common configurations.

Table 3-4: Latency Through Various Transmitter Components/Processes

Block
(1)
Fabric Interface 2 TXUSRCLK2 +
2 TXUSRCLK
Encoding:
8B/10B 3 TXUSRCLK
64B/66B 2-3 TXUSRCLK
Bypass 1 TXUSRCLK
4 TXUSRCLK (±.5) + 1 TXCLK0
TXFIFO
64B/66B Scrambling 1-2 TXCLK0
PMA Convert 1 TXCLK0 (approx.)
(2)
Worst Case Total 4 TXCLK0,
9.5 TXUSRCLK,
2 TXUSRCLK2
(2)
Best Case Total 3 TXCLK0,
6.5 TXUSRCLK,
2 TXUSRCLK2
Notes:
1. Fabric interface has delays in both clock domains. The ratio between these two is shown in
2. Approximate latency when worst/best case latency for each block is used.
3. TXCLK0 is equal in frequency to the TXUSRCLK.

Table 3-5: Latency Through Various Receiver Components/Processes

Block
PMA_PCS 3 RXCLK0
(1)
Interface
CommaDET/Align 2-3 RXCLK0
Bypass 1 RXCLK0
Decoding:
8B/10B 2 RXCLK0 +
2 RXUSRCLK
64B/66B
2 RXCLK0 +
3 RXUSRCLK
Bypass
1 RXCLK0 +
2 RXUSRCLK
RXFIFO
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
1 Byte 2 Byte
1 TXUSRCLK2 +
2 TXUSRCLK
4 TXCLK0,
9.5 TXUSRCLK,
1 TXUSRCLK2
4 TXCLK0,
6.5 TXUSRCLK,
1 TXUSRCLK2
1 Byte 2 Byte
(2)
3 RXCLK0
www.xilinx.com
1-800-255-7778
Table 3-4 and Table 3-5
4 Byte
1 TXUSRCLK2 +
1 TXUSRCLK
(3)
4 TXCLK0,
8.5 TXUSRCLK,
1 TXUSRCLK2
4 TXCLK0,
5.5 TXUSRCLK,
1 TXUSRCLK2
4 Byte
2 or 3 RXCLK0
provide approximate
8 Byte
2 TXUSRCLK2 +
1 TXUSRCLK
4 TXCLK0,
8.5 TXUSRCLK,
2 TXUSRCLK2
4 TXCLK0,
5.5 TXUSRCLK,
2 TXUSRCLK2
Table 3-3.
8 Byte
2 RXCLK0
R
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