Using The Tx Phase Alignment Circuit To Minimize Tx Lane-To-Lane Skew - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
X-Ref Target - Figure 3-22
TXENPMAPHASEALIGN
Note:
is a gated version of PHYSTATUS from the GTX TX. It is recommended that PHYSTATUS indicating
a rate change completion is gated to the Media Access Layer (MAC) during TX phase alignment.
TXENPMAPHASEALIGN must remain asserted after a rate change.

Using the TX Phase Alignment Circuit to Minimize TX Lane-to-Lane Skew

The TX phase-alignment circuit can also be used to minimize skew between GTX
transceivers.
aligning the PMACLK domains of multiple GTX transceivers to a common clock.
Figure 3-23
clock. Before phase alignment, all PMACLKs have an arbitrary phase difference, but after
alignment, the only phase difference is the skew for the common clock, and all data is
transmitted simultaneously as long as the datapath latency is matched.
X-Ref Target - Figure 3-23
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160
TXRATEDONE
PHYSTATUS From GTX
GTXTEST[1]
TXPMASETPHASE
TXRESET
TXRESETDONE
USER_PHYSTATUS or
SYNC_DONE to MAC
Figure 3-22: TX Phase Alignment After Rate Change
PHYSTATUS and USER_PHYSTATUS are used in PCI Express mode. USER_PHYSTATUS
Figure 3-23 shows how the phase-alignment circuit can reduce lane skew by
shows multiple lanes running before and after phase alignment to a common
Skew
Before
Phase Alignment
Figure 3-23: TX Phase Alignment Circuit to Reduce Lane Skew
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16 TXUSRCLK2 Cycles
Required TXUSRCLK2 Cycles
GTX TX
Reduced
Skew
Parallel
Clocks Are
Independent
GTX TX
Virtex-6 FPGA GTX Transceivers User Guide
UG366_c3_30_122810
GTX TX
Parallel Clocks
Are Phase Aligned to
the Same Clock Edge
GTX TX
After
Phase Alignment
UG366_c3_12_051509
UG366 (v2.5) January 17, 2011