Pin Configuration And Function Descriptions - Analog Devices ADAU1961 Manual

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 9. Pin Function Descriptions
Pin No. Mnemonic
1 IOVDD
2 MCLK
3 ADDR0/CLATCH
4 JACKDET/MICIN
5 MICBIAS
6 LAUX
7 CM
8 AVDD
9 AGND
10 LINP
11 LINN
12 RINP
13 RINN
14 RAUX
15 ROUTP
16 ROUTN
17 LOUTN
18 LOUTP
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IOVDD 1
MCLK 2
ADDR0/CLATCH 3
JACKDET/MICIN 4
ADAU1961
MICBIAS 5
LAUX 6
(Not to Scale)
CM 7
AVDD 8
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1961 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
Figure 7. Pin Configuration
1
Type Description
PWR Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which also sets the highest input voltage that should be seen on the digital input pins.
IOVDD should be set to 3.3 V. The current draw of this pin is variable because it is dependent
on the loads of the digital outputs. IOVDD should be decoupled to DGND with a 100 nF
capacitor and a 10 μF capacitor.
D_IN External Master Clock Input.
D_IN I 2 C Address Bit 0 (ADDR0).
SPI Latch Signal (CLATCH). Must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the beginning of the SPI
transaction.
D_IN Detect Insertion/Removal of Headphone Plug (JACKDET).
Digital Microphone Stereo Input (MICIN).
A_OUT Bias Voltage for Electret Microphone.
A_IN Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
A_OUT AVDD/2 V Common-Mode Reference. A 10 μF to 47 μF standard decoupling capacitor should
be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs.
This pin can be used to bias external analog circuits, as long as they are not drawing current
from CM (for example, the noninverting input of an op amp).
PWR 3.3 V Analog Supply for DAC and Microphone Bias. This pin should be decoupled locally to
AGND with a 100 nF capacitor.
PWR Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
A_IN Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2.
A_IN Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2.
A_IN Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2.
A_IN Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2.
A_IN Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
A_OUT Right Line Output, Positive. Biased at AVDD/2.
A_OUT Right Line Output, Negative. Biased at AVDD/2.
A_OUT Left Line Output, Negative. Biased at AVDD/2.
A_OUT Left Line Output, Positive. Biased at AVDD/2.
Rev. 0 | Page 13 of 76
24 DVDDOUT
PIN 1
23 AVDD
INDICATOR
22 AGND
21 MONOOUT
20 LHP
TOP VIEW
19 RHP
18 LOUTP
17 LOUTN
ADAU1961