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Registers
20.9.2.2.2 USB1 Control Register (USB1CTRL)
The USB1 control register (USB1CTRL) allows the CPU to control various aspects of the module. If uint
is set high, then the Mentor controller generic interrupt for USB[9] will be generated (if enabled). This
requires S/W to read the Mentor controller's registers to determine which interrupt USB[0] to USB[7]
occurred. If uint is set low, then the usb20otg_f module will automatically read the Mentor controller's
registers and set the appropriate interrupt USB[0] to USB[7] (if enabled). The generic interrupt for
USB[9] will not be generated.
The USB1 control register is shown in
31
30
29
dis_
dis_
deb
srp
R/W-0h
R/W-0h
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-100. USB1 Control Register (USB1CTRL) Field Descriptions
Bits
Field
31
dis_deb
30
dis_srp
29-06
Reserved
5
soft reset isolation
4
rndis
3
uint
2
Reserved
1
clkfack
0
soft reset
If uint is set high, then the Mentor controller generic interrupt for USB[9] will be generated (if enabled).
This requires S/W to read the Mentor controller's registers to determine which interrupt USB[0] to
USB[7] occurred.
If uint is set low, then the usb20otg_f module will automatically read the Mentor controller's registers
and set the appropriate interrupt USB[0] to USB[7] (if enabled). The generic interrupt for USB[9] will not
be generated.
1888
Universal Serial Bus (USB)
Preliminary
Figure 20-88
Figure 20-88. USB1 Control Register (USB1CTRL)
Reserved
R-0h
Value
Description
Disable the VBUS debouncer circuit fix
Disable the OTG Session Request Protocol (SRP) AVALID circuit fix. When enabled
(=0), this allows additional time for the VBUS signal to be measured against the
VBUS thresholds. The time is specified in the USB1 SRP Fix Time Register.
0
Always read as 0. Writes have no effect.
Soft reset isolation. When high, this bit forces all USB1 signals that connect to the
USBSS to zeros during a soft reset via bit 0 of this register. This bit should be set
high prior to setting bit 0 and cleared after bit 0 is cleared.
Global RNDIS mode enable for all endpoints.
USB non-highlander interrupt enable
0
Highlander
1
Non-highlander
0
Always read as 0. Writes have no effect.
Clock stop fast ack enable.
Software reset of USB1.
Write 0
Write 0 = no action
Write 1
Write 1 = Initiate software reset
Read 0 = Reset done, no action
Read 1 = Reset ongoing
© 2011, Texas Instruments Incorporated
and described in
Table
20-100.
Reserved
R-0h
6
5
4
soft
reset
rndis
isolation
R/W-0h
R/W-0h
www.ti.com
16
3
2
1
0
soft
uint
Rsvd
clkfack
reset
R/W-0h
R-0h
R/W-0h
R/W-0h
SPRUGX9 – 15 April 2011
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