Mcbsp Interface With Communication Processor - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

McBSP Interface With Communication Processor

To support I2S master and slave modes, McBSP2_CLKX, McBSP2_XSYNC, McBSP2_RSYNC, McBSP2_CLKR are

inputs/outputs. They are used unidirectionally for the communication processor connection.

McBSP2 is also an instance of the McBSP module. It can be used either to

support SPI mode or to emulate an I2S serial link.

The McBSP2 interface differs slightly from the McBSP1 interface in that there

is no capability to connect an OMAP5912 external reference clock to it.

McBSP3 is a third instance of the McBSP module. There are two connection

modes for this McBSP:

The first connection mode is a 3-pin interface. The frame synchronization

is internally looped back (FSXO to FSRI), as is the clock. This is the default

reset configuration. In this case, the McBSP3 is half-duplex, master for

transmission, slave for reception. With the assistance of two GPIOs, this

McBSP mode (3 pins) can be configured to connect to an external optical

audio interface device, such as the Sanyo−LC89051V.

In addition, the frame synchronization signal is multiplexed to allow a 4-pin

McBSP interface. The second connection mode is a 4-pin interface. The

frame synchronization is bidirectional, as is the clock. In this case, the

McBSP3 is half-duplex, master/slave for transmission, slave for reception,

enabling an additional I2S emulator.

OMAP5912 Description

Communication processor

Introduction

Table of Contents