Configuring The Spi In Slave Mode - ST STM32F207 Series Reference Manual

RM0033
25.3.2

Configuring the SPI in slave mode

In the slave configuration, the serial clock is received on the SCK pin from the master
device. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data
transfer rate.
Note: It is recommended to enable the SPI slave before the master sends the clock. If not,
undesired data transmission might occur. The data register of the slave needs to be ready
before the first edge of the communication clock or before the end of the ongoing
communication. It is mandatory to have the polarity of the communication clock set to the
steady state value before the slave and the master are enabled.
Follow the procedure below to configure the SPI in slave mode:
Procedure
1. Set the DFF bit to define 8- or 16-bit data frame format
2. Select the CPOL and CPHA bits to define one of the four relationships between the
data transfer and the serial clock (see
and CPHA bits must be configured in the same way in the slave device and the master
device. This step is not required when the TI mode is selected through the FRF bit in
the SPI_CR2 register.
3. The frame format (MSB-first or LSB-first depending on the value of the LSBFIRST bit in
the SPI_CR1 register) must be the same as the master device. This step is not
required when TI mode is selected.
4. In Hardware mode (refer to
connected to a low level signal during the complete byte transmit sequence. In NSS
software mode, set the SSM bit and clear the SSI bit in the SPI_CR1 register. This step
is not required when TI mode is selected.
5. Set the FRF bit in the SPI_CR2 register to select the TI mode protocol for serial
communications.
6. Clear the MSTR bit and set the SPE bit (both in the SPI_CR1 register) to assign the
pins to alternate functions.
In this configuration the MOSI pin is a data input and the MISO pin is a data output.
Transmit sequence
The data byte is parallel-loaded into the Tx buffer during a write cycle.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin. The remaining bits (the 7 bits in 8-bit data frame
format, and the 15 bits in 16-bit data frame format) are loaded into the shift-register. The
TXE flag in the SPI_SR register is set on the transfer of data from the Tx Buffer to the shift
register and an interrupt is generated if the TXEIE bit in the SPI_CR2 register is set.
Receive sequence
For the receiver, when data transfer is complete:
•
The Data in shift register is transferred to Rx Buffer and the RXNE flag (SPI_SR
register) is set
• An Interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register.
Figure 250). For correct data transfer, the CPOL
Slave select (NSS) pin
RM0033 Rev 9
Serial peripheral interface (SPI)
management), the NSS pin must be
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