Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr) - ST STM32F446 Series Reference Manual

RM0390
Bit 9
Bit 8
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 USART6EN: USART6 clock enable
Bit 4 USART1EN: USART1 clock enable
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8EN: TIM8 clock enable
Bit 0 TIM1EN: TIM1 clock enable
6.3.15 RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x6067 90FF
Access: no wait state, word, half-word and byte access.
31 30 29
OTGHS
OTGHS
Res. ULPI
LPEN
LPEN
rw rw
15 14 13
FLITF
Res. Res.
LPEN
rw
ADC2EN: ADC2 clock enable
This bit is set and cleared by software.
0: ADC2 clock disabled
1: ADC2 clock enabled
ADC1EN: ADC1 clock enable
This bit is set and cleared by software.
0: ADC1 clock disabled
1: ADC1 clock enabled
This bit is set and cleared by software.
0: USART6 clock disabled
1: USART6 clock enabled
This bit is set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
This bit is set and cleared by software.
0: TIM8 clock disabled
1: TIM8 clock enabled
This bit is set and cleared by software.
0: TIM1 clock disabled
1: TIM1 clock enabled
28 27 26
Res. Res. Res. Res.
12 11 10
CRC
Res. Res. Res.
LPEN
rw
25 24 23 22
DMA2
Res. Res.
LPEN
rw
9 8 7 6
GPIOH GPIOG
Res.
LPEN LPEN
rw rw
RM0390 Rev 4
Reset and clock control (RCC)
21 20 19 18
BKP
DMA1
Res. Res. SRAM
LPEN
LPEN
rw rw
5 4 3 2
GPIOF GPIOE GPIOD GPIOC
LPEN LPEN LPEN LPEN
rw rw rw rw
17 16
SRAM2 SRAM1
LPEN LPEN
rw rw
1 0
GPIOB GPIOA
LPEN LPEN
rw rw
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