Table 2-6 Relationship Between Value Set At Outcr And Duty - Fujitsu MB89140 Series Hardware Manual

12-BIT MULTIPUL
GENERATOR
(MPG, TIMER 4)
HARDWARE CONFIGURATION
For example, the relationship between the value set at the OUTCR and the
duty with 7F set at the CMCLR is given in Table 2-6 (the output polarity is
H
assumed to be positive (SPOL = 0)).

Table 2-6 Relationship between value Set at OUTCR and Duty

Value set at OUTCR
(00)
H
(01)
H
(02)
H
(03)
H
(7D)
H
(7E)
H
(7F)
H
(80) to (3FF)
H H
For (value set at OUTCR > value set at CMCLR) and (value set at OUTCR
0 and value set at CMCLR = 0), a waveform with a duty of 100% is output.
For (value set at OUTCR = 0 and value set at CMCLR = 0) and (value set at
OUTCR = 0 and value set at CMCLR 0), a waveform with a duty of 0% is
output.
Since the OUTCR and CMCLR have a buffer register, the value of the buffer
can be rewritten before one cycle to change the cycle and duty.
The polarity of the output pulse can be changed by setting the SPOL bit. For
the PWM operation flow, see Figure 2.34.
In the initial state, the timer and prescaler are stopped. The MPG output is in
the reset state. Since the CMCLR and CMCLBR, and the OUTCBR and
OUTCR are connected to each other, simultaneous writing is possible.
The PWM output is started by input of the selected trigger. First, the timer
and prescaler are cleared and the MPG output enters the set state. Then,
the counter starts incrementing.
The MPG output is reset if the values of the OUTCR and counter agree, and
is set if the value of the CMCLR +1 and the value of the timer agree.
If the value of the OUTCR agrees with the value of the CMCLR +1, compari-
son with the value of the CMCLR + 1 proceeds and the MPG output is set.
The effective edge of the external trigger can be selected by setting the
ESL1 and ESL0 bits.
2-65
Output wave form Duty
0%
0.78%
1.56%
2.34%
97.6%
98.4%
99.2%
100%