Execution Cycle Count - Fujitsu MB90895 Series Hardware Manual

APPENDIX
A.5

Execution Cycle Count

The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, correction value
determined by the condition, and the number of cycles for instruction fetch.
I Execution Cycle Count
In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the
program fetches the instruction being executed in word increments. Therefore, intervening in data access
increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count.
In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM,
internal I/O unit, or external data bus causes the clock to the CPU to halt for the cycle count specified by
the CG0 and CG1 bits in the low power consumption mode control register. For the cycle count required
for instruction execution in CPU intermittent operation mode, therefore, add the corresponding "access
count x halt cycle count" as a correction value to the normal execution cycle count.
I Calculating the Execution Cycle Count
Table A.5-1, Table A.5-2, Table A.5-3 show the execution cycle counts, and correction value.
Table A.5-1 Execution Cycle Counts in Each Addressing Mode
Code
00 to 07
08 to 0B
0C to 0F
10 to 17
18 to 1B
1C
1D
1E
1F
*:(a) is used for (cycle count) and B (correction value) in A.8 F
634
Operand
Execution cycle count in each
Ri
RWi See the instruction list.
RLi
@RWj
@RWj+
@RWi+disp8
@RWi+disp16
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
*
(a)
addressing mode
2
4
2
2
4
4
2
1
2
MC-16LX Instruction List.
Register access count
in each addressing
mode
See the instruction list.
1
2
1
1
2
2
0
0