Dmac Ch0 To Ch4 Transfer Source/Transfer Destination Address Setting Registers - Fujitsu FR60 Hardware Manual

CHAPTER 16 DMA CONTROLLER (DMAC)
16.2.3 DMAC ch0 to ch4 Transfer Source/Transfer Destination
Address Setting Registers
The DMASA0 to 4 registers and DMADA0 to 4 registers control the operation of the
DMAC channels. A separate register is provided for each channel.
■ Functions of the DMASA0 to 4 Bits and DMADA0 to 4 Bits
The functions of the DMASA0 to 4 bits and DMADA0 to 4 bits are shown below.
bit 31
bit 15
(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX Bit)
bit 31
bit 15
(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX Bit)
DMASA0 to 4 and DMADA0 to 4 are a group of registers used to store transfer source and transfer
destination addresses. The length of each register is 32 bits.
[Bits 31 to 0] DMASA (DMA Source Addr): Transfer source address setting
These bits set the transfer source address.
[Bits 31 to 0] DMADA (DMA Destination Addr): Transfer destination address setting
These bits set the transfer destination address.
If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated
address counter and then the address is counted according to the settings for the transfer operation.
When the DMA transfer is completed, the contents of the counter buffer are written back to this register
and then DMA ends. Thus, the address counter value during DMA operation cannot be read.
All registers have a dedicated reload register. When the register is used for a channel that is enabled for
reloading of the transfer source/transfer destination address register, the initial value is automatically
written back to the register when the transfer is completed. Other address registers are not affected.
• When reset: Not initialized.
• These bits are readable and writable. For this register, be sure to access these bits as 32-bit data.
• If these bits are read during transfer, the address before the transfer is read. If they are read after
transfer, the next access address is read. Because the reload value cannot be read, it is not possible to
read the transfer address in real time.
488
30 29 28 27
14 13 11 11
30 29 28 27
14 13 11 11
26 25 24 23
DMASA [31 : 16]
10 9 8 7
DMASA [15 : 0]
26 25 24 23
DMADA [31 : 16]
10 9 8 7
DMADA [15 : 0]
22 21 20 19
6 5 4 3
22 21 20 19
6 5 4 3
18 17 16
2 1 0
18 17 16
2 1 0