Fig. 2.16 Orfe Flag Set Timing; Fig. 2.17 Tdre Flag Set Timing; Fig. 2.18 Transfer Data Format (Synchronous Transfer) - Fujitsu F2MC-8L Family series Hardware Manual

Peripherals
Data
RDRF = 1
ORFE
SIN interrupt
SODR write
TDRE
SOUT interrupt
SOUT output
SCK
SI, SO

Fig. 2.18 Transfer Data Format (Synchronous Transfer)

HARDWARE CONFIGURATION
Stop
(Overrun error)

Fig. 2.16 ORFE Flag Set Timing

b. Transmission
When the next data is ready to write after data written to the SODR (serial
output data register) is transferred to the interrupt shift register, the TDRE
(transmit data register empty) flag is set and an interrupt request is output
to the CPU.
Interrupt request output to CPU
S 0 1 2
S: Start bit 0 to 7: Data bitsP: Stop bit

Fig. 2.17 TDRE Flag Set Timing

(c) Transfer data format
The UART can handle only NRZ (non-return-to-zero)-type data. The
relationship between transmitter/receiver clocks and data is shown in the
figure below.
0 1 0 1
Start LSB
Transmitted data is 01001101
Data
RDRF = 0
ORFE
SIN interrupt
3 4 5 6 7 P P
1 0 0 1 0
MSB Stop
(mode 1) or 101001101 (mode 3)
B B
2– 47
Stop
(Framing error)
S 0 1 2 3
1 1
Varies with mode
Stop Stop