Fig. 2.5 Rule For Translating Real Addresses At General-Purpose Register Area - Fujitsu MB89140 Series Hardware Manual

CPU
HARDWARE CONFIGURATION
The RP indicates the address of the current register bank and the contents
of the RP; the real addresses are translated as shown in Figure 2.5.
'0' '0' '0' '0'
Source
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
address
Fig. 2.5 Rule for Translating Real Addresses at
General-purpose Register Area
The CCR has bits indicating the results of operations and transfer data con-
tents, and bits controlling the CPU operation when an interrupt occurs.
H-flag H-flag is set when a carry or a borrow out of bit 3 into bit 4
is generated as a result of operations; it is cleared in other
cases. This flag is used for decimal-correction instruc-
tions.
I-flag An interrupt is enabled when this flag is 1 and is disabled
when it is 0. The I-flag is 0 at reset.
IL1 and IL0 These bits indicate the level of the currently-enabled inter-
rupt. The CPU executes interrupt processing only when
an interrupt with a value smaller than the value indicated
by this bit is requested.
IL1 IL0 Interrupt level
0 0
0 1
1 0
1 1
N-flag The N-flag is set when the most significant bit is 1 as a
result of operations; it is cleared when the MSB is 0.
Z-flag Z-flag is set when the bit is 0 as a result of operations; it is
cleared in other cases.
V-flag V-flag is set when a two's complement overflow occurs as
a result of operations; it is reset when an overflow does
not occur.
C-flag C-flag is set when a carry or a borrow out of bit 7 is gener-
ated as a result of operations; it is cleared in other cases.
When the shift instruction is executed, the value of the
C-flag is shifted out.
2-7
R P
'0' '0' '0' '1' R4 R3 R2 R1 R0
High and low
High
1
2
3 Low = No interrupt
Lower bits of OP code
b2 b1 b0