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CHAPTER 4 BUS INTERFACE
4.3.2
Area Mode Register 0 (AMD0)
This register specifies the operating mode of chip select area 0 (space excluding the
areas specified by ASR1 to ASR5 and AMR1 to AMR5). Area 0 is selected when the
system is reset.
I Area mode register 0 (AMD0)
The configuration of Area mode register 0 (AMD0) is as follows:
AMD0
Address
: 000620
H
[Bits 4 and 3]: Bus Width bits (BW1, BW0)
BW1 and BW0 specify the bus width of area 0.
BW1
0
0
1
1
Note:
The initial values of BW1 and BW0 are 0, however, the levels of the MD1 and MD0 pins
are read until writing to the MODR during reading.
104
7
6
5
4
BW1
BW0
0
8 bits
1
16 bits
0
Reserved
1
Reserved
3
2
1
BW0
WTC2
WTC1
WTC0
Bus width
Initial value
Access
0
- --00111
R/W
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