Overview - Xilinx Virtex-7 FPGA VC7215 Getting Started Manual

VC7215 IBERT Getting Started Guide

Overview

This document provides a procedure for setting up the Virtex®-7 FPGA VC7215 GTH
Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs required to run the IBERT
demonstrations are stored in three Secure Digital (SD) memory cards that are provided with
the VC7215 board. The demonstration shows the capabilities of the Virtex-7 XC7VX690T
FPGA GTH transceiver.
The VC7215 board is described in detail in VC7215 Virtex-7 FPGA GTH Transceiver
Characterization Board User Guide (UG972)
The IBERT demonstrations operate one GTH Quad at a time. The procedure consists of:
1. Setting Up the VC7215 Board, page 6
2. Extracting the Project Files, page 7
3. Connecting the GTH Transceivers and Reference Clocks, page 8
4. Configuring the FPGA, page 14
5. Setting Up Vivado Design Suite, page 16
6. Starting the SuperClock-2 Module, page 19
7. Viewing GTH Transceiver Operation, page 25
8. Closing the IBERT Demonstration, page 26
VC7215 Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015
[Ref 1].
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