Chapter 4: Receiver; Rx Overview - Xilinx Virtex-6 FPGA User Manual

Receiver

RX Overview

This chapter shows how to configure and use each of the functional blocks inside the GTX
receiver (RX). Each GTX transceiver includes an independent receiver, made up of a PCS
and a PMA.
traces on the board into the PMA of the RX, into the PCS, and finally into the FPGA logic.
X-Ref Target - Figure 4-1
PLL
RX
DFE
EQ
RX
CDR
RX OOB
SIPO
RX-PMA
The key elements within the GTX RX are:
1.
2.
3.
4.
5.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Figure 4-1 shows the blocks of the RX. High-speed serial data flows from
From TX Parallel
To TX Parallel Data
Data (Near-End
(Far-End PMA Loopback)
PCS Loopback)
Pattern
Checker
Polarity
Over-
sampling
Figure 4-1: GTX RX Block Diagram
RX Analog Front End, page 184
RX Out-of-Band Signaling, page 192
RX Equalizer, page 194
RX CDR, page 204
RX Fabric Clock Output Control, page 207
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To TX Parallel Data
(Far-End PCS Loopback)
Loss of Sync
RX PIPE Control
Comma
Detect
and
RX Status Control
Align
Gearbox
Elastic
Buffer
10B
/8B
Chapter 4
FPGA
RX
Interface
RX
RX-PCS
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