Chapter 4: Receiver; Rx Analog Front End - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver

RX Analog Front End

The RX analog front end (AFE) is a high-speed, current-mode, input differential buffer
with calibrated termination resistors.
X-Ref Target - Figure 4-1
Board
~100 nF
~100 nF
Different conditions must be considered when configuring the RX AFE.
examples of those conditions.
Table 4-1: RX AFE Board Interface Configurations
Transceiver Power Transceiver GND
Pins Connected to Referenced with
Power Link Partner
– N
– –
N Y
Y Y
Y Y
Y Y
104
FPGA
MGTHAVCCRX_[L,R]
Nominal
50W
Nominal
MGTHAVCCRX_[L,R]
50W
Figure 4-1: Structure of the RX AFE
RX Configuration
RX Driven by Coupling
Link Partner (AC/DC)
– –
– DC
Y AC
Y AC
Y AC
Y AC
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Figure 4-1 shows the structure of the RX AFE.
Nominal
V = 0.7V
CM
Nominal
66 pF
GND
Transceiver RX Powered
Configured via Down Via
Bitstream Attributes
– –
– –
– –
N N
N
(configuration
N
ongoing and
not complete)
Y Y
Virtex-6 FPGA GTH Transceivers User Guide
Nominal
1KW
Nominal
V = 0.7V
CM
Nominal
1KW
GND
UG371_c4_02_020210
Table 4-1 shows
Recom-
Comments
mended
Link partners should be
GND referenced, otherwise
N
the relative offsets can
damage the FPGA.
Only AC coupling mode is
N
supported
Y
The receiver common mode
Y
becomes MGTHAVTT. The
single-ended swing
absolute value is limited by
Y
the maximum voltage value
of the RXP/RXN signals
specified in DS152,
Virtex-6 FPGA Data Sheet:
Y DC and Switching
Characteristics.
UG371 (v2.0) February 16, 2010