Tx Polarity Control; Tx Gray Encoder - Xilinx Virtex UltraScale+ FPGAs User Manual

TX PRBS pattern generator is disabled and the TX is driven based on the CH[0/1]_TXDATA
input.

TX Polarity Control

If TXP and TXN differential traces are accidentally swapped on the PCB, the differential data
transmitted by the GTM transceiver TX is reversed. One solution is to invert the parallel data
before serialization and transmission to offset the reversed polarity on the differential pair. The
TX polarity control can be accessed through the CH0_TXPOLARITY and CH1_TXPOLARITY
input from the interconnect logic interface. The TX polarity control is driven High to invert the
polarity of outgoing data.
Ports and Attributes
The following table defines the ports required for TX polarity control.
Table 40: TX Polarity Control Ports
Port
1
CH0_TXPOLARITY
1
CH1_TXPOLARITY
Notes:
1. CH[0/1]_TXPOLARITY can be tied High if the polarity of TXP and TXN needs to be reversed.

TX Gray Encoder

GTM transmitters in UltraScale+ devices support two types of binary encoding options: linear
coding and Gray coding. By using Gray coding, only one bit error per symbol is made for incorrect
decisions, thus reducing the bit-error rate by more than 33%. The following figure illustrates the
differences between linear coding and Gray coding.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In CH0_TXUSRCLK2
In CH1_TXUSRCLK2
Chapter 3: Transmitter
Description
The CH0_TXPOLARITY port is used to invert the
polarity of the outgoing data for channel 0:
0: Not inverted. TXP is positive, and TXN is
negative.
1: Inverted. TXP is negative, and TXN is
positive.
The CH1_TXPOLARITY port is used to invert the
polarity of the outgoing data for channel 1:
0: Not inverted. TXP is positive, and TXN is
negative.
1: Inverted. TXP is negative, and TXN is
positive.
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