Analog-To-Digital Converter (Adc) - Analog Devices AD9866 Instructions Manual

35
33
31
29
27
25
23
21
19
50 MSPS MEASURED
17
50 MSPS CALCULATED
15
48 64 80 96 112
TARGET-DECIMAL EQUIVALENT
Figure 73. Measured and Calculated f
for f = 50 MSPS and 80 MSPS
ADC
The following scaling factor can be applied to the previous
formula to compensate for the RxPGA gain setting on f
Scale Factor = 1 − (RxPGA in dB)/382
This scaling factor reduces the calculated f
increased. Applications that need to maintain a minimum cut-
off frequency, f , for all RxPGA gain settings should first
−3 dB_MIN
determine the scaling factor for the highest RxPGA gain setting
to be used. Next, the f
−3 dB_MIN
factor to normalize to the 0 dB RxPGA gain setting (f
Equation 8 can then be used to calculate the target value.
The LPF frequency response shows a slight sensitivity to
temperature, as shown in Figure 74. Applications sensitive to
temperature drift can recalibrate the LPF by rewriting the target
value to Register 0x08.
35
30
F
OUT
F
OUT
25
20
15
96 112 128 144
TARGET-DECIMAL EQUIVALENT
Figure 74. Temperature Drift of f
80 MSPS MEASURED
80 MSPS CALCULATED
128 144 160 176 192 208 224
vs. Target Value
−3 dB
−3 dB
as the RxPGA is
−3 dB
should be divided by this scale
−3 dB_0 dB
ACTUAL 80MHz AND –40 ° C
ACTUAL 80MHz AND +25 ° C
ACTUAL 80MHz AND +85 ° C
F
OUT
160 176 192 208 240
224
for f = 80 MSPS and RxPGA = 0 dB
−3 dB ADC

ANALOG-TO-DIGITAL CONVERTER (ADC)

The AD9866 features a 12-bit analog-to-digital converter
(ADC) capable of up to 80 MSPS. Referring to Figure 68, the
ADC is driven by the SPGA stage, which performs both the
sample-and-hold and the fine gain adjust functions. A buffer
amplifier (not shown) isolates the last CPGA gain stage from
the dynamic load presented by the SPGA stage. The full-scale
input span of the ADC is 2 V p-p, and depending on the PGA
gain setting, the full-scale input span into the SPGA is
adjustable from 1 V to 2 V in 1 dB increments.
A pipelined multistage ADC architecture is used to achieve high
sample rates while consuming low power. The ADC distributes
the conversion over several smaller A/D subblocks, refining the
conversion with progressively higher accuracy as it passes the
results from stage to stage on each clock edge. The ADC typi-
cally performs best when driven internally by a 50% duty cycle
:
clock. This is especially the case when operating the ADC at
high sample rate (55 MSPS to 80 MSPS) and/or lower internal
(9)
bias levels, which adversely affect interstage settling time
requirements.
The ADC sampling clock path also includes a duty cycle
restorer circuit, which ensures that the ADC gets a near 50%
duty cycle clock even when presented with a clock source with
poor symmetry (35/65). This circuit should be enabled, if the
).
ADC sampling clock is a buffered version of the reference signal
appearing at OSCIN (see the Clock Synthesizer section) and if
this reference signal is derived from an oscillator or crystal
whose specified symmetry cannot be guaranteed to be within
45/55 (or 55/45). This circuit can remain disabled, if the ADC
sampling clock is derived from a divided down version of the
clock synthesizer's VCO, because this clock is near 50%.
The ADC's power consumption can be reduced by 25 mA, with
minimal effect on its performance, by setting Bit 4 of Register 0x07.
Alternative power bias settings are also available via Register 0x13,
as discussed in the Power Control and Dissipation section.
Lastly, the ADC can be completely powered down for half-
duplex operation, further reducing the AD9866's peak power
consumption.
Rev. A | Page 35 of 48
AD9866