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UFP—Problem (User) Fetch Permission
Bit 26:
0 = Subpage 0 (address[20:21]=00) problem fetch is not permitted.
1 = Subpage 0 (address[20:21]=00) problem fetch is permitted.
Bit 27:
0 = Subpage 1 (address[20:21]=01) problem fetch is not permitted.
1 = Subpage 1 (address[20:21]=01) problem fetch is permitted.
Bit 28:
0 = Subpage 2 (address[20:21]=10) problem fetch is not permitted.
1 = Subpage 2 (address[20:21]=10) problem fetch is permitted.
Bit 29:
0 = Subpage 3 (address[20:21]=11) problem fetch is not permitted.
1 = Subpage 3 (address[20:21]=11) problem fetch is permitted.
PV—Page Validity
0 = Page is invalid.
1 = Page is valid.
G—Guarded
0 = Unguarded storage.
1 = Guarded storage.
11.7 INTERRUPTS
11.7.1 Implementation-Specific Instruction TLB Miss
The implementation-specific instruction TLB miss interrupt occurs when MSR
is an attempt to fetch an instruction from a page whose effective page number cannot be
found in the instruction translation lookaside buffer. The software tablewalk code is
responsible for loading the translation information of the missed page from the translation
table that resides in the memory. Refer to Section 11.8.1.1 Translation Reload Examples
for more information.
11.7.2 Implementation-Specific Data TLB Miss
The implementation-specific data TLB miss interrupt occurs when MSR
an attempt to access a page whose effective page number cannot be found in the data
translation lookaside buffer. The software tablewalk code is responsible for loading the
translation information of the missed page from the translation table that resides in the
memory. Refer to Section 11.8.1.1 Translation Reload Examples for more information.
MOTOROLA
MPC823e REFERENCE MANUAL
Memory Management Unit
=1 and there
IR
=1 and there is
DR
11-47
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