Motorola MPC823e Reference Manual page 119

The frequency for the GCLKx system clock is:
VCOOUT
freq
GCLKx = --------------------------------------------------------------
freq
DFNH DFNL 1
( )or 2 (
2
The frequency for the GCLKx_50 system clock is:
VCOOUT
freq
GCLKx_50 = --------------------------------------------------------------
freq
DFNH DFNL 1
( )or 2 (
2
CLKOUT is derived from GCLK2_50. It defaults to VCOOUT, which is the user-defined
system frequency (25-75MHz). CLKOUT can drive at full-strength, half-strength, or it can be
disabled. The strength of the drive is controlled in the system clock and reset control
register. Disabling or decreasing the strength of CLKOUT reduces power consumption,
noise, and electromagnetic interference on the printed circuit board. When the SPLL is
acquiring lock, the CLKOUT signal is disabled and remains in a low state.
GCLK1
5.3.4.2 THE BAUD RATE GENERATOR CLOCK. The baud rate generator clock
(BRGCLK) is used by the four baud rate generators of the communication processor module
and by the memory controller refresh counter. It defaults to VCOOUT, which is the
user-defined system frequency (25-75MHz). The baud rate generator clock allows the baud
rate generators to continue operating at a fixed frequency, even when the rest of the
MPC823e is operating at a reduced frequency. Refer to Section 16.8 The Baud Rate
Generators for more information about using the baud rate generator clock to save power.
VCOOUT
DFBRG
MOTOROLA
+
)
1
×
---------------------------
+
EBDF 1 +
)
EBDF
PHASE
GCLK2_50
Figure 5-10. CLKOUT Divider
BRGCLK
Figure 5-11. BRGCLK Divider
MPC823e REFERENCE MANUAL
Clocks and Power Control
CLKOUT
CPM, UPM,
(REFRESH
TIMER)
5-19