Motorola MPC823e Reference Manual page 381

PTB—Periodic Timer B
This field affects the periodic timer B and determines the timer period using the following
equation:
System Clock (MHz) Service Duration (µs)
PTB = -------------------------------------------------------------------------------------------------------------------- -
×
2 DFBRG
2
NCS is an integer between 1 and 8 that represents the number of enabled chip-selects that
select this UPM. The DFBRG field is the division factor for the BRGCLK, which can be
divided by 1 (default), 4, 16, or 64 and is programmed in the SCCR (described in
Section 5.2.1 System Clock and Reset Control Register).
For example, for DRAM to maintain data integrity an access or refresh must occur every
15.6µs. Use the equation above to determine the PTB value for UPMB to perform memory
refresh. Given that you have a 25MHz system clock with the required service rate of 15.6µs,
a periodic timer prescaler equal to 32, and a DFBRG field that is equal to 0, then the PTB
value must be (25 × 15.6) / (2
per service, use the TLFB field.
PTBE—Periodic Timer B Enable
This bit allows the periodic timer B to request service.
0 = Periodic timer B is disabled.
1 = Periodic timer B is enabled.
AMB—Address Multiplex Size B
This field specifies the number of address lines to be output on the bus at the first clock of
the memory cycle (see Table 15-7 on page 15-60 for more information). The AMX field of
the RAM array entry controls the output of the address lines, as shown in Table 15-3
(page 15-37). For example, these address lines can be used to connect to the DRAM
devices that require row and columns to be multiplexed on the same pin.
Bits 12 and 15—Reserved
These bits are reserved and must be set to 0.
DSB—Disable Timer Period
This bit guarantees a minimum time between accesses to the same memory bank if it is
controlled by the UPMB. The TODT bit turns on the disable timer in the RAM array and,
when expired, the UPMB allows the machine access to issue a memory pattern to the same
memory region. Accesses to different memory regions using two or more chip-selects can
be handled by this same UPMB, assuming they have the same timing. The maximum
disable period is four clock cycles. When switching to a different bank that requires more
than four clock cycles, you must add more UPM RAM word to meet your time requirement.
MOTOROLA
×
× ×
Prescaler (PTP) NCS
× 32× 1) = 12. If you want to perform more than one refresh
2×0
MPC823e REFERENCE MANUAL
Memory Controller
15-23