Fixed-Point Arithmetic Instructions; The Load/Store Processor; Fixed-Point Load With Update And Store; Fixed-Point Load And Store Multiple Instructions - Motorola MPC823e Reference Manual

7.1.8.1 MOVE TO/FROM SYSTEM REGISTER INSTRUCTIONS. Move to/from invalid
special registers in which spr
the processor is in problem state (user mode). For a list of all implemented special registers,
refer to Section 6.4.1 Control Registers .
7.1.8.2 FIXED-POINT ARITHMETIC INSTRUCTIONS. If you try to perform any of the
following divisions using the divw[o][.] instruction
÷
0x80000000 -1
÷
<anything> 0
then, the contents of RT are 0x80000000 and if Rc =1, the contents of the bits in the CR field
0 are LT = 1, GT = 0, EQ = 0, and SO is set to the correct value.
In the cmpi , cmp , cmpli , and cmpl instructions, the L bit is applicable for 64-bit
implementations. For the MPC823e, if L = 1 the instruction form is invalid. The core ignores
this bit and, therefore, the behavior when L = 1 is identical to the valid form instruction with
L = 0.

7.1.9 The Load/Store Processor

The load/store processor supports all of the 32-bit implementation fixed-point PowerPC
load/store instructions in the hardware.
7.1.9.1 FIXED-POINT LOAD WITH UPDATE AND STORE WITH UPDATE
INSTRUCTIONS. For load with update and store with update instructions where RA =0, the
EA is written into R0. For load with update instructions where RA = RT, RA is boundedly
undefined.
7.1.9.2 FIXED-POINT LOAD AND STORE MULTIPLE INSTRUCTIONS. For these types
of instructions, EA must be a multiple of four. If it is not, the system alignment error handler
is invoked. For a lmw instruction (if RA is in the range of registers to be loaded), the
instruction completes normally. RA is then loaded from the memory location as follows:
RA <- MEM(EA+(RA-RT)*4, 4)
Note: The instruction form is invalid if RA is in the range of registers to be loaded or if
RA = 0.
7.1.9.3 FIXED-POINT LOAD STRING INSTRUCTIONS. Load string instructions behave
the same as load multiple instructions, with respect to invalid format in which RA is in the
range of registers to be loaded. If RA is in the range, it is updated from memory.
Note: The instruction forms are invalid if RA is in the range of registers to be loaded or
if RA = 0 (i.e. R0). For lswx only, the instruction form is invalid if RD=RA or
RD=RB.
MOTOROLA
=1 invokes the privilege instruction error interrupt handler if
0
MPC823e REFERENCE MANUAL
PowerPC Architecture Compliance
7-3