Motorola MPC823e Reference Manual page 730

Communication Processor Module
16.9.19.9 CONFIGURING THE SCCx ASYNC HDLC PARAMETERS. The SCCx ASYNC
HDLC parameters can be configured as described in Section 16.9 The Serial
Communication Controllers through Section 16.9.8 Handling Interrupts In the SCCs ,
except for the changes in the following registers. When you are in asynchronous HDLC
mode, some of the bits in the GSMR_x and general DSR have different meanings.
For the SCCx in ASYNC HDLC mode, the general SCCx mode high and low register
(GSMR_x) bit descriptions remain the same, except for:
• RFW—RX FIFO Width (GSMR_H)
0 = must not be used.
1 = Low-latency operation. The RX FIFO is 8 bits wide and the receive FIFO is one
quarter its normal size (8 bytes). This allows data to be written to the data buffer
each time a character is received, without forcing you to wait for 32 bits to be
received. You must choose this configuration for character-oriented protocols like
UART and asynchronous HDLC.
• TDCR—Transmit Divide Clock Rate (GSMR_L)
These bits determine the divider rate of the transmitter. If the DPLL is not used, you
must choose the 1 × value. In asynchronous UART or HDLC mode, you must choose
8 × , 16 × , or 32 × . You must program these bits to equal the RDCR field in most
applications.
00 = Do not use.
01 = 8 × clock mode (do not use for IrLAP).
10 = 16 × clock mode.
11 = 32 × clock mode (do not use for IrLAP).
• RDCR—Receive DPLL Clock Rate (GSNR_L)
These bits determine the divider rate of the receive DPLL. If the DPLL is not used, you
must choose the 1 × value. In asynchronous UART or HDLC mode, you must choose
8 × , 16 × , or 32 × . You must program these bits to equal the TDCR field in most
applications.
00 = Do not use.
01 = 8 × clock mode (do not use for IrLAP).
10 = 16 × clock mode.
11 = 32 × clock mode (do not use for IrLAP).
The data synchronization register (DSR) is reserved in asynchronous HDLC mode. It must
be set to 0x7E7E.
16-276 MPC823e REFERENCE MANUAL MOTOROLA