Motorola MPC823e Reference Manual page 928

Communication Processor Module
2
16.13.7.5 I C BAUD RATE GENERATOR REGISTER. The 8-bit, memory mapped,
2
read/write I C baud rate generator (I2BRG) register sets the divide ratio of the baud rate
generator. This register is set to all ones at hard reset.
I2BRG
BIT 0 1
FIELD
RESET 1 1
R/W
ADDR
DIV— Division Ratio 0–7
This field specifies the divide ratio of the baud rate generator divider in the I
generator. The output of the prescaler is divided by 2 x (DIV + 3 + (2 x FLT)) and the clock
has a 50% duty cycle. The FLT bit is in the I2MOD register.
Note: The minimum value for DIV is three if the digital filter is disabled (FLT=0) and six
if it is enabled (FLT=1).
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16.13.7.6 I C COMMAND REGISTER. The 8-bit read/write I
2
is used to start I C operation.
I2COM
BIT 0 1
FIELD STR
RESET 0
R/W R/W
ADDR
STR—Start Transmit
2
When the I C controller is in master mode, setting this bit to 1 causes the I
start transmitting data from the I
is in slave mode, setting the STR bit to 1 when the I
transmit data register from the I
address byte that matches the slave address with the R/W bit set to 1. The STR bit is always
read as a zero.
16-474
2 3 4
DIV
1 1 1
R/W
(IMMR & 0xFFFF0000) + 0x868
2 3 4
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x86C
2
C transmit buffers if they are ready. When the I
2
C controller is idle causes it to load the
2
C transmit buffer and start transmitting when it receives an
MPC823e REFERENCE MANUAL
5 6
1 1
2
C clock
2
C command (I2COM) register
5 6
M/S
R/W
2
C controller to
2
C controller
MOTOROLA
7
1
7
0