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6.4.1.2.3 Fixed-Point Exception Cause Register. The following table provides the bit
assignments for the fixed-point exception cause register (XER). The bits are based on the
final result produced by executing an instruction.
XER
BIT
0
1
2
FIELD
SO
OV
CA
RESET
0
0
0
R/W
R/W
R/W
R/W
BIT
16
17
18
FIELD
RESET
R/W
SO—Summary Overflow
This bit is set when an instruction other than mtspr sets the OV bit. Once SO is set, it stays
that way until an mtspr or mcrxr instruction clears it. It is not altered by compare instructions
or other instructions that cannot overflow. SO is cleared and OV is set when an mtspr
instruction is executed, which supplies the zero values for these bits.
OV—Overflow
When this bit is set, it indicates that an overflow has occurred during the execution of an
instruction. The add, subtract, and negate instructions with OE equal to 1, set this bit if the
carry out of the MSB is not equal to that carry out of the MSB+1. The multiply low and divide
instructions with OE equal to 1, set this bit if the result cannot be represented in 64 bits
(mulld, divd, divdu) or 32 bits (mullw, divw, divwu). The OV bit is not altered by compare
instructions that cannot overflow, except mtspr to the XER and mcrxr.
CA—Carry
This bit is set during execution of the following instructions. It is not altered by compare
instructions or by other instructions that cannot carry, except shift right algebraic, mtspr to
the XER, and mcrxr.
•
Add carrying, subtract from carrying, add extended, and subtract from extended
instructions set CA if there is a carry out of the MSB. Otherwise, it is cleared.
•
The shift right algebraic instructions set CA if any 1 bits have been shifted out of a
negative operand. Otherwise, it is cleared.
Bits 3–24—Reserved
These bits are reserved and must be set to 0.
BCNT—Byte Count for Load/Store String Operations
This field specifies the number of bytes to be transferred by a lswx or stswx instruction.
MOTOROLA
3
4
5
6
7
19
20
21
22
23
RESERVED
0
R/W
MPC823e REFERENCE MANUAL
8
9
10
11
12
RESERVED
0
R/W
24
25
26
27
28
BCNT
0
R/W
The PowerPC Core
13
14
15
29
30
31
6-23
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