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16.13.3.1.1 Master Write. To begin a write operation to a slave device that contains
internal addresses, you must prepare a TX data buffer that is N+2 bytes in length. The first
byte contains the 7-bit device address followed by the write bit asserted (R/W = 0). The
second byte contains the internal base address of the write. The remaining N bytes contain
the data to be written to the slave. The slave device will process the N bytes of data
sequentially, starting at the specified base address.
S
T
A
R
T
SDA
DEVICE ADDR
NOTE: DATA AND ACK ARE REPEATED N TIMES.
Figure 16-128. Byte Write to Device with Internal Addresses
To begin a master write operation to a slave device that does not contain internal addresses,
you must prepare a TX data buffer that is N+1 bytes long. The first byte contains the 7-bit
slave device address followed by the write bit asserted (R/W = 0). The remaining N bytes
contain the data to be written to the slave.
SDA
NOTE: DATA AND ACK ARE REPEATED N TIMES.
Figure 16-129. Byte Write to Device without Internal Addresses
Next, when communicating to either slave device, the W and L bits must be set in the TX
buffer descriptor. Set the I bit in the TX buffer descriptor to enable the transmission status
to be updated in the I2CE register and to enable I
the TX buffer descriptor to prepare the buffer for transmission. The final step is to set the
STR bit in the I2COM register to initiate transmission. The data starts transmitting once the
SDMA channel loads the transmit FIFO with data and the I
Note: Some slave devices, such as serial E2PROMs, may have a minimum write cycle
time. For these devices, the I
after a write before initiating the next read or write. The required delay must be
implemented in software.
MOTOROLA
A
C
K
W
BASE ADDR
S
T
A
R
A
T
C
DEVICE ADDR
W
K
DATA BYTE
2
C interrupts to the core. Set the R bit in
2
C controller must wait a minimum amount of time
MPC823e REFERENCE MANUAL
Communication Processor Module
S
T
O
A
A
P
C
C
K
DATA BYTE
K
S
T
O
A
P
C
K
2
C bus is not busy.
16-459
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