Motorola MPC823e Reference Manual page 457

Communication Processor Module
The block diagram of the communication processor module is illustrated in Figure 16-1.
U - BUS
INTERRUPT
BUS INTERFACE SDMA
CONTROLLER
INTERNAL BUS
RISC
TIMERS
MICROCONTROLLER
SEQUENCER ROM
DUAL-PORT
PARALLEL I/O PORTS
RAM
REGISTER FILE
ALU CRC MAC
BAUD RATE GENERATORS
PERIPHERAL BUS
2
USB SCC3 SMC1 SMC2 SPI I C
SCC2
SERIAL INTERFACE AND TIME-SLOT ASSIGNER
Figure 16-1. CPM Block Diagram
MOTOROLA MPC823e REFERENCE MANUAL 16-3