Motorola MPC823e Reference Manual page 752

Communication Processor Module
16.9.20.5.4 Middle-Speed IrDA Programming Example. Middle-speed infrared
programming is very similar to SCC2 synchronous HDLC programming. The parameter
RAM programming and the RX and TX buffer descriptors are the same as in the SCC2
HDLC. All of the SCC2 synchronous registers and the infrared registers must be initialized.
The following list is an initialization sequence for a middle-speed infrared channel assuming
that an external clock is provided. The CLK3 pin is used for the infrared receiver and
transmitter.
1. Configure the port A pins to enable the TXD2 and RXD2 pins. Write bits 13 and 12 of
the PAPAR with ones. Write bits 13 and 12 of the PADIR with zeros. Write bits 13 and
12 of the PAODR with zeros.
2. Configure port A to enable the CLK3 pin. Write PAPAR bit 5 with a one. Write zero to
bit 5 of the PADIR.
3. Connect the CLK3 pin to the SCC2 using the serial interface. In the SICR, write 110
to the R2CS and T2CS fields.
4. Connect the SCC2 to the NMSI (its own set of pins). Clear the SC2 bit in the SICR.
5. Write the SDCR with the appropriate arbitration ID.
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RX and TX
buffer descriptors in the dual-port RAM. Assuming one RX buffer descriptor at the
beginning of dual-port RAM and one TX buffer descriptor following that RX buffer
descriptor, set RBASE to 0x2000 and TBASE to 0x2008.
7. Program the CPCR to execute the INIT RX AND TX PARAMS command for the
SCC2.
8. Write 0x18 to the RFCR and 0x18 to the TFCR for normal operation.
9. Write the maximum number of bytes per receive buffer to the MRBLR. For this case,
assume 256 bytes, so MRBLR equals 0x0100. The value of 256 was chosen to allow
an entire receive frame to fit into one receive buffer.
10. Write CRC_P with 0xFFFFFFFF to comply with 16-bit CRC32.
11. Write CRC_C with 0xDEBB20E3 to comply with 16-bit CRC32.
12. Clear DISFC, CRCEC, ABTSC, NMARC, and RETRC for the sake of clarity.
13. Write MFLR with 0x0100 to make the maximum frame size 256 bytes.
14. Write RFTHR with 0x0001 to allow interrupts after each frame.
15. Write HMASK with 0x0000 to allow all addresses to be recognized.
16. Clear HADDR1, HADDR2, HADDR3, and HADDR4 for clarity.
17. Initialize the RX buffer descriptor. Assume the RX data buffer is at 0x00001000 in main
memory. Write 0xB000 to RX_BD_Status. Write 0x0000 to RX_BD_Length (not
required-done for instructional purposes only). Write 0x00001000 to RX_BD_Pointer.
18. Initialize the TX buffer descriptor. Assume the TX data frame is at 0x00002000 in main
memory and contains five 8-bit characters. Write 0xBC00 to TX_BD_Status. Write
0x0005 to TX_BD_Length. Write 0x00002000 to TX_BD_Pointer.
19. Write 0xFFFF to the SCCE–HDLC to clear any previous events.
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