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9.4.4 Unlocking the Entire Instruction Cache
The UNLOCK ALL command is used to unlock the entire instruction cache. This operation
is privileged and any attempt to perform it when the core is in the problem state (MSR
results in a program interrupt. It is performed on all cache lines. If a line is locked, it is
unlocked and operates as a regular valid cache line. If a line is not locked or if it is invalid,
no operation occurs. To unlock the whole cache, set the UNLOCK ALL command in the
IC_CST. This command has no associated error cases. The instruction cache performs this
instruction in one clock cycle. To accurately calculate the latency of this instruction, bus
latency must be taken into consideration.
9.4.5 Inhibiting the Instruction Cache
In the MPC823e, there are two ways to inhibit the cache—using the MMU cache-inhibit
attribute or the cache disable mode. To disable the instruction cache, set the CACHE
DISABLE command in the IC_CST. This operation is privileged and any attempt to perform
it when the core is in the problem state (MSR
command has no error cases that you need to check.
To enable the instruction cache, set the CACHE ENABLE command in the IC_CST. This
operation is privileged and any attempt to perform it when the core is in the problem state
(MSR
=1) results in a program interrupt. This command has no error cases that you need
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to check. When fetching from cache-inhibited regions the full line is brought to the internal
burst buffer. Instructions that originate in a cache-inhibited region and are stored in the burst
buffer can be sent to the MPC823e core no more than once before being refetched. In the
memory management unit, a memory region can be programmed as cache-inhibited. When
changing a memory region to be cache inhibited, you must unlock all previously locked lines
containing code that originated in this memory region, invalidate all lines containing code
that originated in this memory region, and execute an isync instruction.
Note: Failure to follow these steps causes code from cache-inhibited regions to be left
inside the cache and any reference to these regions will result in a cache hit. If
a reference to a cache-inhibited region results in a cache hit, the data is sent to
the core from the cache and not from memory.
When the MPC823e asserts the FRZ signal, it indicates that the MPC823e is under debug
and all fetches from the cache are treated as if they were from the cache-inhibited memory
region. For more information on cache debug support, refer to Section 9.9 Debug Support.
MOTOROLA
=1) results in a program interrupt. This
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MPC823e REFERENCE MANUAL
Instruction Cache
=1)
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9-11
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