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Table 15-9. GPL_x5 Signal (Pin) Behavior
MACHINE
MACHINE
CONTROLLING
CONTROLLING
THE
THE SLAVE
MEMORY
ACCESS
ACCESS
CLOCK CYCLE
GPCM
x
UPMA
First
Second, Third...
UPMB
First
Second, Third...
UPMB
Second, Third...
MOTOROLA
G5LA
G5LS
G5T4
G5T3
(ORx)
(ORx)
(RAM
(RAM
WORD)
WORD)
N/A
N/A
x
x
x
0
x
x
1
x
x
0
x
1
x
x
0
x
1
0
0
x
x
1
1
0
x
x
1
0
x
0
x
1
x
x
0
x
1
1
x
0
x
1
x
x
0
x
1
MPC823e REFERENCE MANUAL
Memory Controller
GPL_x5 BEHAVIOR
AT THE CONTROLLING
CLOCK EDGE
GPL_A5 and GPL_B5 do not change their
value.
GPL_A5 is driven low at the falling edge of
GCLK1.
GPL_A5 is driven high at the falling edge
of GCLK1.
GPL_A5 is driven low at the falling edge of
GCLK2 in the current UPM cycle.
GPL_A5 is driven high at the falling edge
of GCLK2 in the current UPM cycle.
GPL_A5 is driven low at the falling edge of
GCLK1 in the current UPM cycle.
GPL_A5 is driven high at the falling edge
of GCLK1 in the current UPM cycle.
GPL_B5 is driven low at the falling edge of
GCLK1.
GPL_B5 is driven high at the falling edge
of GCLK1.
GPL_A5 is driven low at the falling edge of
GCLK1.
GPL_A5 is driven high at the falling edge
of GCLK1.
GPL_B5 is driven low at the falling edge of
GCLK2 in the current UPM cycle.
GPL_B5 is driven high at the falling edge
of GCLK2 in the current UPM cycle.
GPL_B5 is driven low at the falling edge of
GCLK1 in the current UPM cycle.
GPL_B5 is driven high at the falling edge
of GCLK1 in the current UPM cycle.
GPL_A5 is driven low at the falling edge of
GCLK2 in the current UPM cycle.
GPL_A5 is driven high at the falling edge
of GCLK2 in the current UPM cycle.
GPL_A5 is driven low at the falling edge of
GCLK1 in the current UPM cycle.
GPL_A5 is driven high at the falling edge
of GCLK1 in the current UPM cycle.
15-71
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