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Communication Processor Module
DATA LENGTH
This field represents the number of bytes the SCCx HDLC controller transmits from this
buffer descriptor data buffer. It is never modified by the communication processor module.
The value of this field must be greater than zero. The SCCx HDLC controller writes these
bits after it finishes transmitting the associated data buffer.
TX DATA BUFFER POINTER
This field contains the address of the associated data buffer and can be even or odd. The
buffer can reside in internal or external memory. This value is never modified by the
communication processor module. The SCCx HDLC controller writes these bits after it
finishes transmitting the associated data buffer.
16.9.16.11 SCCx HDLC EVENT REGISTER.When a serial communication controller is in
HDLC mode, the 16-bit, memory-mapped SCCx event register is referred to as the SCCx
HDLC event register (SCCE–HDLC). Since each protocol has specific requirements, the
SCCE bits are different for each implementation. This register is used to report events
recognized by the HDLC channel and to generate interrupts. When an event is recognized,
the SCCx HDLC controller sets the corresponding bit in this register. Interrupts generated
by this register can be masked in the SCCM–HDLC register. An example of interrupts that
can be generated using the HDLC protocol is illustrated in Figure 16-81.
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MPC823e REFERENCE MANUAL
MOTOROLA
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