Table of Contents
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LIST OF ILLUSTRATIONS (Continued)
Figure
Number
18-1. LCD Panel ...................................................................................................... 18-2
18-2. LCD Subsystem ............................................................................................. 18-3
18-3. Passive Interfaces .......................................................................................... 18-4
18-4. Active (TFT) Interface .................................................................................... 18-5
18-5. The MPC823e LCD System ........................................................................... 18-6
18-6. LCD Controller Block Diagram ....................................................................... 18-7
18-7. LCD Functional Module ................................................................................. 18-8
18-8. Grayscale Generation .................................................................................. 18-11
18-9. Color Generation .......................................................................................... 18-12
18-10. Single-Scan and Dual-Scan LCD Panels ..................................................... 18-15
18-11. Passive Interface Timing Diagram ............................................................... 18-16
18-12. Active Interface Timing Diagram .................................................................. 18-18
18-13. Color RAM Transparent Translation for One-Bit Per Pixel Mode ................ 18-31
18-14. Color RAM Entries for Two Bits Per Pixel Mode .......................................... 18-32
18-15. Color RAM Entries for Four Bits Per Pixel (Grayscale) ................................ 18-34
19-1. Typical MPC823e Video System ................................................................... 19-1
19-2. Video Controller Block Diagram ..................................................................... 19-3
19-3. Output Timing Example ................................................................................. 19-4
19-4. Video RAM Array Block Diagram ................................................................. 19-16
19-5. Interlaced NTSC Format .............................................................................. 19-20
19-6. NTSC Horizontal Timing .............................................................................. 19-21
19-7. Interlaced PAL Format ................................................................................. 19-24
19-8. PAL Horizontal Timing ................................................................................. 19-25
20-1. Watchpoint and Breakpoint Support in the Core .......................................... 20-10
20-2. Example 2 False Detect on Watchpoint/Breakpoint ..................................... 20-14
20-3. Instruction Support General Structure ......................................................... 20-16
20-4. Load/Store Support General Structure ........................................................ 20-19
20-5. Relationship Between the CPU and Debug Mode ....................................... 20-21
20-6. Debug Mode Logic Implementation ............................................................. 20-23
20-7. Debug Mode Reset Configuration Timing Diagram ..................................... 20-25
20-8. Development Port/Background Development Mode Connector Pinout
Options ........................................................................................................ 20-30
xl
Title
Section 18
LCD Controller
Section 19
Video Controller
Section 20
Development Capabilities and Interface
MPC823e REFERENCE MANUAL
Page
Number
MOTOROLA
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