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External Bus Interface
13.4.7.2 ADDRESS BUS. The 26-bit address bus consists of address bits 6–31 and Bit 6
is most-significant. The bus is byte addressable, so each address can address one or more
bytes. The address and its attributes are driven on the bus with the TS signal and stay valid
until the bus master received a TA signal from the slave. To distinguish the individual byte,
the slave device must observe the TSIZx signals.
Note: Although this is a 32-bit machine, only 26 of the bits are visible outside the chip.
13.4.7.3 TRANSFER ATTRIBUTES. The transfer attributes consist of the RD/WR,
BURST, TSIZx, ATx, STS, and BDIP signals. These signals, except for the BDIP, are
available at the same time as the address bus.
13.4.7.3.1 Read/Write Signal. When the RD/WR signal is high it indicates a read access
and when it is low it indicates a write access.
13.4.7.3.2 Burst Signal. The BURST signal and the address are driven by the bus master
at the beginning of the bus cycle to indicate that the transfer is a burst transfer. The burst
size is always 16 bytes. With a 32-bit port size, the burst includes 4 beats. When its port size
is 16 bits and controlled by the internal memory controller, the burst includes 8 beats. When
its port size is 8 bits and controlled by the internal memory controller, the burst includes 16
beats. The MPC823e bus supports critical data word first for burst. The order of the
wraparound goes back to the critical word. For example, assuming data 2 is the critical word:
• Case burst of four beats:
data 2
data 3
data 0
• Case burst of eight beats:
data 2
data 3
data 4
13-32
data 1
.........
data 7
data 0
MPC823e REFERENCE MANUAL
data 1
MOTOROLA
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