Motorola MPC823e Reference Manual page 703

Microprocessor for mobile computing
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W—Wrap (Final Buffer Descriptor in Table)
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer
has been used, the communication processor module transmits data from the first
buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table are programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
I—Interrupt
0 = No interrupt is generated after this buffer is serviced.
1 = The TXB or TXE bit in the SCCE–HDLC register is set when this buffer is serviced
by the SCCx HDLC controller. These bits can cause interrupts if they are enabled.
L—Last
0 = This is not the last buffer in the frame.
1 = This is the last buffer in the frame.
TC—TX CRC
This bit is valid only when the L bit is set. Otherwise, it is ignored.
0 = Transmit the closing flag after the last data byte. This setting can be used to send
a bad CRC after the data for testing purposes.
1 = Transmit the CRC sequence after the last data byte.
CM—Continuous Mode
0 = Normal operation.
1 = The R bit is not cleared by the communication processor module after this buffer
descriptor is closed, thus allowing the associated data buffer to be automatically
retransmitted next time the communication processor module accesses this buffer
descriptor. However, the R bit is cleared if an error occurs during transmission,
regardless of how the CM bit is set.
UN—Underrun
This bit indicates when the SCCx HDLC controller encounters a transmitter underrun
condition while transmitting the associated data buffer. The SCCx HDLC controller writes
these bits after it finishes transmitting the associated data buffer.
CT—CTS Lost
This bit indicates when CTSx in NMSI mode or layer 1 grant is lost in GCI mode during frame
transmission. If data from more than one buffer is currently in the FIFO when this error
occurs, this bit is set in the currently open TX buffer descriptor. The SCCx HDLC controller
writes these bits after it finishes transmitting the associated data buffer.
MOTOROLA
MPC823e REFERENCE MANUAL
Communication Processor Module
16-249

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