Motorola MPC823e Reference Manual page 672

Communication Processor Module
UM—UART Mode
This field selects the protocol that is implemented over the ASYNC channel and it can be
modified on-the-fly.
00 = Normal UART operation. Multidrop mode is disabled and an idle-line wake-up is
selected. In the idle-line wake-up mode, the UART receiver is reenabled by
receiving a character of all ones.
01 = Manual multidrop mode. In multidrop mode, an additional address/data bit is
transmitted with each character. The multidrop asynchronous modes are
compatible with the MC68681 DUART, MC68HC11 SCI, DSP56000 SCI, and
Intel 8051 serial interface. The UART receiver is reenabled when the last bit
received in the character is a one. This means that the received character is an
address that has to be processed by all inactive processors. The SCCx UART
controller receives the address character and writes it to a new buffer. The core
then compares the written address with its own address and decides whether to
ignore or process the characters.
10 = Reserved.
11 = Automatic multidrop mode. In this mode, the communication processor module
automatically checks the address of the incoming address character using the
UADDR1 and UADDR2 parameter RAM values and accepts or discards the data
that follows the address.
FRZ—Freeze Transmission
This bit allows you to stop the UART transmitter and resume transmission from the same
point at a later time.
0 = Normal operation. If the SCCx UART controller was previously frozen, the UART
resumes transmission from the next character in the same buffer that was frozen.
1 = The SCCx UART controller completes transmission of any data already transferred
to the UART FIFO (the number of characters depends on the TFL bit in the
GSMR_H) and then freezes. After this bit is reset, transmission proceeds from the
next character.
RZS—Receive Zero Stop Bits
This bit configures the UART receiver to receive data without any stop bits. This
configuration is useful in V.14 applications in which SCCx UART controller data is supplied
synchronously and all stop bits of a particular character can be omitted for the purpose of
cross-network rate adaptation. RZS must only be set if the SYN bit is also set.
0 = The receiver operates normally, but at least one stop bit is required between
characters. A framing error is issued when there is a missing stop bit and a break
status is set if a character with all-zero data bits is received with a zero stop bit.
1 = The receiver continues if a missing stop bit is detected. If the stop bit is a zero, the
next bit is considered the first data bit of the next character. A framing error is
issued if a stop bit is missing, but a break status is only reported after back-to-back
reception of two break characters without stop bits.
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