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The PowerPC Core
6.3.4.1 RESTARTABILITY AFTER AN INTERRUPT
Most of the interrupt cases in the core are always restartable. Some interrupts may be
unable to be restarted because they can be recognized when the machine status
save/restore 0 and 1 registers (SRR0 and SRR1) are busy. Such interrupts in the PowerPC
architecture are known as system reset and machine check.
All other interrupt types defined in the architecture must always be restartable. By
convention, no interrupt generating instruction must be executed between the start of an
interrupt handler and the save of the registers altered by any interrupt or between restore of
these registers and the execution of the rfi instruction. These registers being the SRR0 and
SRR1 registers or the data address register (DAR) and data storage interrupt status register
(DSISR) for some interrupt types.
External interrupts are also masked in these areas. In the core, two implementation-specific
interrupt types can have this characteristic—debug port unmaskable interrupt and
breakpoint interrupt in nonmaskable mode. Since there might be a situation in which it is
preferable to be restartable, such as in the mentioned implementation-specific interrupts, a
mechanism is defined to notify the interrupt handler code whether it is in a restartable state.
The mechanism uses a bit within the machine state register (MSR) called the recoverable
interrupt bit (MSR
). The MSR
RI
the interrupt is restartable. This bit does not need to be checked on interrupt types that are
restartable by convention, except those previously mentioned. The MSR
similar behavior as the external interrupt enable bit (MSR
MSR
is copied to its shadow in the SRR1 register (like the MSR) and cleared. Every time
RI
an rfi instruction is executed, MSR
addition, it can be altered by the software via the mtmsr instruction. The MSR
intended to be set by the interrupt handler software after saving the machine state, (registers
SRR0, SRR1, DAR, and DSISR if needed) and cleared by the interrupt handler software
before retrieving the machine state.
In critical code sections where MSR
busy, MSR
must be left asserted. In these cases, if an interrupt occurs it is restartable. To
RI
facilitate the software manipulation of the MSR
commands implemented as move to special register. The following table defines these
special register mnemonics. A write of any data to these locations performs the operation
specified in the following table. Any read from these locations is treated like any other
unimplemented instruction and, therefore, results in an implementation-dependent software
emulation interrupt.
6-10
shadow bit in the SRR1 register indicates whether or not
RI
is copied from its shadow in the SRR1 register. In
RI
is negated but the SRR0 and SRR1 registers are not
EE
and MSR
RI
MPC823e REFERENCE MANUAL
bit follows a
RI
). Every time an interrupt occurs,
EE
RI
bits, the core includes special
EE
bit is
MOTOROLA
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