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Memory Controller
15.6.1 External Master Examples
A synchronous example interconnection in which an external master and the MPC823e can
both share access to a DRAM bank is illustrated in Figure 15-37. Notice that CS1, UPMA,
and GPL_A5 were chosen to assist in the control of DRAM bank accesses. To perform burst
accesses initiated by the external master or MPC823e using this configuration, the A[28:30]
signals are connected to the multiplexer controlled by GPL_A5. Figure 15-38 illustrates the
timing behavior of control signals when an external master to a DRAM bank initiates a burst
read access. The state of the GPL_A5 pin in the first clock cycle of the memory device
access is determined by the value of the G5LS bit in the corresponding option register. In
this example, the accessed critical word is addressed at A[28:29] = 10, which then
increments and wraps around to the word before the critical word (01) for subsequent beats
of this burst access.
CS1
BSx
Figure 15-37. Synchronous External Master Interconnect Example
15-72
DRAM
BANK
GPL_A5
MULTIPLEXER
A[6:31]
D[0:31]
R/W
TS
BURST
TA
TSIZx
BI
BR
BG
BB
MPC823e REFERENCE MANUAL
MOTOROLA
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