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Communication Processor Module
16.6.3.7 STARTING IDMA. Once the channel has been initialized with all parameters
required for a transfer operation, IDMA is started by setting the DREQx bit in the port C
special option (PCSO) register. Once DREQx has been set, the channel is active and
accepts operand transfer requests through the channel's corresponding DREQx pin. When
the first valid external request is recognized, IDMA arbitrates for the bus and the DREQx pin
input is ignored until the DREQx bit is set in the PCSO register. IDMA1 is higher than IDMA2.
The software can suspend channel transfer operation at any time by clearing the DREQx bit
in the PCSO register. In response, any operand transfer in progress will be completed and
the bus will be released. No further bus cycles are started while the DREQx bit remains
cleared. During this time, the core can access IDMA internal registers to determine the
status of a channel or to alter operation. When the DREQx bit is set again, if a transfer
request is pending, IDMA arbitrates for the bus and continues normal operation. Interrupts
from IDMA are sent to the interrupt controller. In the interrupt handler, the unmasked bits in
the IDSRx must be cleared (by writing them with a 1) to negate the interrupt request to the
CPM interrupt controller.
16.6.3.8 REQUESTING IDMA TRANSFERS. Once IDMA has been started, transfers to
IDMA can be requested. These transfers are initiated by externally generated requests from
an external device using the DREQx pin in conjunction with the activation of the DREQx bit
of the PCSO register.
16.6.3.9 LEVEL-SENSITIVE MODE. For external devices that require very high data
transfer rates, level-sensitive mode allows IDMA to use a maximum bandwidth to service
the device. In this mode, the DREQx pin input to IDMA is level-sensitive and sampled at
rising edges of the clock to determine when a valid request is asserted by the device. The
device requests service by asserting the DREQx pin and leaving it asserted as long as it
needs service.
Each time IDMA issues a bus cycle to either read or write the device, it outputs the SDACKx
signal. The device is either the source or destination of the transfers, as determined by the
TYPE field of the DCMR. SDACKx is the acknowledgment of the original burst request given
on the DREQx pin, which must be negated during the SDACKx active period to guarantee
that no further cycles are performed. Burst mode in the context of the DREQx pin actually
means back-to-back DMA cycles. Burst in the context of the bus means burst cycle. The
DMA always uses bursts at the memory width.
16.6.3.10 EDGE-SENSITIVE MODE. For external devices that generate a pulsed signal for
each operand to be transferred, edge-sensitive mode must be used. In edge-sensitive
mode, IDMA moves one operand for each falling edge of the DREQx pin input. DREQx is
sampled at each rising edge of the clock to determine when a valid request is asserted by
the device. When IDMA detects a falling edge on the DREQx pin, a request becomes
pending and remains as such until it is serviced by IDMA. Further falling edges on the
DREQx pin are ignored until the request starts being serviced, which results in one operand
being transferred. Each time IDMA issues a bus cycle to read or write the device, it outputs
the SDACKx signal. The device is either the source or destination of the transfers, as
determined by the TYPE field of the DCMR. Thus, SDACKx is the acknowledgment of the
original cycle steal request given on the DREQx pin.
MOTOROLA
MPC823e REFERENCE MANUAL
16-101
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