Motorola MPC823e Reference Manual page 536

Communication Processor Module
5. Write 0xFFFF to the TER2. This clears the TER2 of any bits that might have been set.
6. Write 0x00040000 to the CIMR. This enables a timer 2 interrupt in the CPM interrupt
controller and initializes the CICR.
7. Write 0x0010 to the TGCR. This enables timer 2 to begin counting.
To implement the same function with a 32-bit timer using timers 1 and 2, follow these steps:
1. Write 0x0080 to the TGCR. This cascades timers 1 and 2 and puts them in a reset
state.
2. Write 0x001A to the TMR2. This enables the timer 2 prescaler to divide by 1 and the
clock source to the general system clock. It also enables an interrupt when the
reference value is reached and restarts the timer to continuously generate 10ms
interrupts.
3. Write 0x0000 to the TMR1. This enables timer 1 to use the output of timer 2 as its input
(default of TMR1).
4. Write 0x0000 to the TCN1 and 0x0000 to the TCN2. This initializes the count of the
combined timers 1 and 2 to zero (default of TMR1) by using one 32-bit data move to
TCN1.
5. Write 0x0000 to the TRR1 and 0x00FA to the TRR2. This initializes the reference
value of the combined timers 1 and 2 to 250 by using one 32-bit data move to TRR1.
6. Write 0xFFFF to the TER2. This clears the TER2 of any bits that might have been set.
7. Write 0x00040000 to the CIMR. This enables the timer 2 interrupt in the CPM interrupt
controller and initializes the CICR.
8. Write 0x0091 to the TGCR. This enables timers 1 and 2 to begin counting, but leaves
them in cascaded mode.
16.5 THE SDMA CHANNELS
The MPC823e has two physical serial DMA (SDMA) channels. One is controlled by the
RISC microcontroller and the other is controlled by the LCD controller. The RISC
microcontroller implements 12 virtual SDMA channels and each one is associated with a
serial channel transmitter or receiver. Four channels are associated with the full-duplex
serial communication controllers and the other eight are used for the serial peripheral
2
interface, I C controller, and serial management controllers. Each channel is permanently
assigned to service either the receive or transmit operation of a serial communication
controller, serial management controller, serial peripheral interface, or I
from these controllers can be routed to the external RAM (path 1) or the internal dual-port
RAM (path 2) with the U-Bus. Figure 16-36 illustrates the paths of the data flow.
On a path 1 access, the U-Bus and external system bus must be acquired by the SDMA
channel. On a path 2 access, only the U-Bus needs to be acquired and the access is not
seen on the external system bus, unless the MPC823e is configured into the "show cycles"
mode of the system interface unit. Thus, transfers on the U-Bus occur at the same time that
other operations occur on the external system bus.
16-82 MPC823e REFERENCE MANUAL
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C controller. Data
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