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PowerPC Architecture Compliance
7.3.7.3.10 Implementation-Dependent Software Emulation Interrupt. An
implementation-dependent software emulation interrupt occurs as a result of one of the
following conditions:
• When executing any unimplemented instruction, including all illegal and
unimplemented optional and floating-point instructions.
• When executing a mtspr or mfspr that specifies an on-core unimplemented register,
regardless of SPR
.
0
• When executing a mtspr or mfspr that specifies an off-core unimplemented register
and SPR
=0 or MSR
0
to Section 7.3.7.3.6 Program Interrupt.
In addition, the following registers are set:
SRR0—Save/Restore Register 0
Set to the effective address of the instruction that caused the interrupt.
SRR1—Save/Restore Register 1
1–4
Set to 0.
10–15
Set to 0.
Other
Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
MSR—Machine State Register
IP
No change.
ME
No change.
LE
Bits are copied from the ILE.
Other
Set to 0.
Execution resumes at offset x'01000' from the base address indicated by MSR
Note: The exception 1000 implementation-dependent software emulation is triggered
when an unimplemented opcode is being decoded.
7.3.7.3.11 Implementation-Specific Instruction TLB Miss Interrupt. This type of
interrupt occurs if MSR
IR
page number cannot be translated by TLB. The following registers are set:
SRR0–Save/Restore Register 0
Set to the effective address of the instruction that caused the interrupt.
7-12
=0 (no program interrupt condition). For more information, refer
PR
=1 and you try to fetch an instruction from a page whose effective
MPC823e REFERENCE MANUAL
.
RI
.
IP
MOTOROLA
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