Motorola MPC823e Reference Manual page 446

Memory Controller
15.7.2 Page Mode Extended Data-Out DRAM Interface Example
The configuration for a 1M, 32-bit wide memory system using two 256K x 16-bit page mode
extended data-out (EDO) DRAMs is illustrated in Figure 15-51. Also shown is the physical
connection between UPMB and the EDO DRAMs. The CS2 signal that is controlled by the
base register is connected to both of the RAS signals. The BS_B[0:1] signals are mapped
to the lower DRAM (D[0:15]) and the BS_B[2:3] signals are mapped to the upper DRAM
(D[16:31]). For this connection, GPL_B1 is connected to the memory device OE pins. The
refresh rate is calculated based on a 25MHz baud rate generator clock and the DRAM that
requires a 512-cycle refresh every 8ms.
MPC823E
BS_B[0:3]
CS2
R/W
GPL_B1
A[21:29]
D[0:31]
Figure 15-51. EDO DRAM Interface Connection
Follow these steps to configure a system for EDO DRAM:
1. Determine the system architecture, which includes the MPC823e and the memory
system as shown in the example in Figure 15-52.
2. Use the blank worksheet (Figure 15-58) to draw the timing diagrams for all the memory
cycles associated with your architecture. You can also use, as a reference, the various
timing diagrams in Figure 15-52 through Figure 15-57.
3. Translate the timing diagrams into RAM words for each type of memory access. The
bottom half of the figures represent the RAM array contents that handle each of the
possible cycles and each column represents a different word in the RAM array. A
blank cell in each figure indicates a "don't care" bit, which is typically programmed to
logic 1 to conserve power.
15-88
2
RAS
BS_B0
CASL
BS_B1
CASH
WE
MT4C16270
256K X 16
OE
A[0:8]
D[0:15]
D[0:15]
MPC823e REFERENCE MANUAL
2
RAS
BS_B2
CASL
BS_B3
CASH
WE
MT4C16270
256K X 16
OE
A[0:8]
D[0:15]
D[16:31]
16
16
MOTOROLA