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Clocks and Power Control
The system responds quickly to an interrupt that does not come from the interrupt controller.
The wake-up time from normal low, doze high, doze low, or sleep mode is between three
and four VCOOUT clocks. For example, it could take 60-80ns to wake up in a 75MHz
system. The level-sensitive interrupt from the interrupt controller is defined as a wake-up
interrupt. It is only negated after the interrupt source bit is cleared. Any of the real-time clock,
periodic interrupt timer, timebase, or decrementer interrupts can set the TMIST bit in the
PLPRCR. The MPC823e clock module recognizes this interrupt as a pending interrupt when
the TMIST bit is set. Therefore, the TMIST bit must be cleared before you enter any low-
power mode other than normal high mode.
The wake-up time for all interrupt sources from the interrupt controller is measured in actual
GCLK1 clocks. Once the interrupt is recognized, it takes between two and four GCLK1
clocks for the MPC823e to reach normal high mode. For example, it could take between
10.24µs and 20.48µs to wake up in a 75MHz system where DFNL = 111 (divided by 256).
In normal and doze modes when the CSRC bit is set, the system toggles between the low
and high frequencies. One of the following conditions must be met before you can switch
from normal low mode to normal high mode.
• The communication processor module must be active (CPM_ACT)
• A pending interrupt from the interrupt controller must be recognized (INTERRUPT)
• The POW bit in the MSR must be cleared (normal operation) (POW)
If none of these conditions are met, the CSRC bit is set, and the interrupt status bits are
reset, then the system automatically switches back to normal low mode. If the
communication processor module is active, the system automatically switches from doze
low mode to doze high mode. On the other hand, when the communication processor
module is idle and the CSRC bit is set, then the system automatically switches back to doze
low mode. A pending interrupt from the interrupt controller transfers the system from doze
mode to normal high mode. The MPC823e exits deep-sleep mode and enters normal high
mode when a wake-up interrupt from the interrupt controller, real-time clock, periodic
interrupt timer, timebase, or decrementer is recognized.
In deep-sleep mode the SPLL is disabled and, therefore, the wake-up time from this mode
is a maximum of 500 OSCM clocks. In 1-to-1 mode, the wake-up time can be a maximum
of 1,000 EXTCLK clocks. For example, if the SPLL input frequency is 32kHz, the wake-up
time is a maximum of 15.6ms and if it is 4MHz in 1-to-1 mode, the wake-up time is a
maximum of 125 µ s.
To exit power-down mode and enter normal high mode, the HRESET pin must be asserted
by external logic when the TEXP pin is asserted. The TEXPS bit in the PLPRCR is
automatically set when a wake-up interrupt from the real-time clock, periodic interrupt timer,
timebase, or decrementer occurs. HRESET must be asserted longer than the time it takes
the power supply to wake up, plus the time it takes for the SPLL to reach lock condition.
Another way to exit power-down mode is to assert HRESET when the TEXP pin is negated
and the TEXPS bit is cleared. This causes the MPC823e to automatically assert the TEXP
pin, which sets the TEXPS bit, and enter normal high mode.
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MPC823e REFERENCE MANUAL
MOTOROLA
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