Table of Contents
Advertisement
LIST OF ILLUSTRATIONS (Continued)
Figure
Number
5-18. MPC823e Low-Power Mode Flowchart ......................................................... 5-29
6-1.
Block Diagram of the Core ............................................................................... 6-3
6-2.
Instruction Flow Conceptual Diagram .............................................................. 6-3
6-3.
Basic Instruction Pipeline Timing Diagram ...................................................... 6-4
6-4.
Sequencer Data Path ....................................................................................... 6-5
6-5.
History Buffer Queue ....................................................................................... 6-9
6-6.
Load/Store Unit Functional Block Diagram .................................................... 6-26
6-7.
Number of Bus Cycles Needed For Unaligned, Single Register
Fixed-Point Load/Store Instructions ............................................................... 6-28
6-8.
Number of Bus Cycles Needed For String Instruction Execution .................. 6-30
8-1.
Example of a Data Cache Load ....................................................................... 8-4
8-2.
Example of a Writeback Arbitration .................................................................. 8-5
8-3.
Another Example of a Writeback Arbitration .................................................... 8-5
8-4.
Example of a Private Writeback Bus Load ....................................................... 8-6
8-5.
Example of an External Load ........................................................................... 8-7
8-6.
Example of a Full History Buffer ...................................................................... 8-8
8-7.
Example of Branch Folding .............................................................................. 8-9
8-8.
Example of Branch Prediction ........................................................................ 8-10
9-1.
Instruction Cache Organization Block Diagram ............................................... 9-3
9-2.
Cache Data Path Block Diagram ..................................................................... 9-4
10-1. Data Cache Organization ............................................................................... 10-2
10-2. Cache Data Path Block Diagram ................................................................... 10-3
11-1. Block Diagram of Effective-to-Real Address Translation For 4K Pages ........ 11-3
xxxii
Title
Section 6
The PowerPC Core
Section 8
Intruction Execution Timing
Section 9
Instruction Cache
Section 10
Data Cache
Section 11
Memory Management Unit
MPC823e REFERENCE MANUAL
Page
Number
MOTOROLA
Advertisement
Table of Contents
