Motorola MPC823e Reference Manual page 800

Communication Processor Module
16.9.23.4 SCCx ETHERNET EVENT REGISTER. When a serial communication controller
is in Ethernet mode, the 16-bit memory-mapped SCCx event register is referred to as the
SCCx Ethernet event register (SCCE–Ethernet). Since each protocol has specific
requirements, the SCCE bits are different for each implementation. This register is used to
generate interrupts and report events recognized by the Ethernet channel. When an event
is recognized, the SCCx Ethernet controller sets the corresponding bit in the SCCE–
Ethernet register. Interrupts generated by this register can be masked in the SCCM–
Ethernet register. An example of interrupts that can be generated in the Ethernet protocol is
illustrated in Figure 16-111.
A bit is cleared by writing a 1(writing a zero has no effect) and more than one bit can be
cleared at a time. All unmasked bits must be cleared before the communication processor
module clears the internal interrupt request. This register is cleared at reset and can be read
at any time.
SCCE–ETHERNET
BIT 0 1 2
FIELD
RESET
R/W
ADDR
Bits 0–7 and 9–10—Reserved
These bits are reserved and must be set to 0.
GRA—Graceful Stop Complete
If set, this bit indicates that a graceful stop, initiated by the GRACEFUL STOP TRANSMIT
command, is now complete. This bit is set as soon the transmitter finishes any frame in
progress when the command is issued. It is set immediately if no frame is in progress when
the command is issued.
TXE—TX Error
This bit indicates that an error has occurred on the transmitter channel.
RXF—RX Frame
This bit indicates that a complete frame has been received on the Ethernet channel.
BSY—Busy Condition
This bit indicates when a frame is received and discarded due to a lack of buffers.
16-346
3 4 5 6 7
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0xA30
MPC823e REFERENCE MANUAL
8 9 10 11 12
GRA RESERVED TXE RXF
0 0 0 0
R/W R/W R/W R/W
13 14 15
BSY TXB RXB
0 0 0
R/W R/W R/W
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