Motorola MPC823e Reference Manual page 397

Figure 15-19 illustrates the timing for TRLX = 0 when an external asynchronous master
accesses SRAM. The TA signal remains asserted with the WEx and OE signals until the AS
signal is negated by the external master.
CLOCK
ADDRESS
AS
TA
CS
WE
OE
DATA
Figure 15-19. Asynchronous External Master, GPCM-Handled
When an external asynchronous master performs an access to a memory device via the
general-purpose chip-select machine in the memory controller, the CSNT bit in the option
register is configured as "don't care".
MOTOROLA
Memory Access Timing (TRLX = 0)
MPC823e REFERENCE MANUAL
Memory Controller
15-39