Motorola MPC823e Reference Manual page 594

Communication Processor Module
16.7.5.5 SERIAL INTERFACE STATUS REGISTER. The 8-bit serial interface status
register (SISTR) lets you know which part of the serial interface RAM is the current-route
RAM. The value of this register is only valid when the corresponding bit in the SICMR is
cleared.
SISTR
BIT 0 1
FIELD CRORA CROTA
RESET 0 0
R/W R R
ADDR
CRORA—Current Route of TDMA Receiver
This bit is valid in the RAM division mode (RDM field in the SIGMR = 01).
0 = The current-route receiver RAM is in address 0–63 when the serial interface
supports TDMA.
1 = The current-route receiver RAM is in address 64–127 when the serial interface
supports TDMA.
CROTA—Current Route of TDMA Transmitter
This bit is valid in the RAM division mode (RDM field in the SIGMR = 01).
0 = The current-route transmitter RAM is in address 128–191 when the serial interface
supports TDMA.
1 = The current-route transmitter RAM is in address 192–255 when the serial interface
supports TDMA.
CRORB—Current Route of TDMB Receiver
This bit is valid in the RAM division mode (RDM field in the SIGMR = 11).
0 = The current-route receiver RAM is in address 64-95 when the serial interface
supports TDMB.
1 = The current-route receiver RAM is in address 96-127 when the serial interface
supports TDMB.
CROTB—Current Route of TDMB Transmitter
This bit is valid in the RAM division mode (RDM field in the SIGMR = 11).
0 = The current-route transmitter RAM is in address 192-223.
1 = The current-route transmitter RAM is in address 224-255.
Bits 4–7—Reserved
These bits are reserved and must be set to 0.
16-140
2 3 4
CRORB CROTB
0 0
R R
(IMMR & 0xFFFF0000) + 0xAE6
MPC823e REFERENCE MANUAL
5 6 7
RESERVED
0
R
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